Chemical mechanical polishing (CMP) has been increasingly used in the semiconductor fabrication industry to planarize the surfaces of integrated circuit chips, thin-film substrates, and thick-film substrates one or more times during the fabrication process. For this purpose, two major objectives are sought: good local planarity of the polished surface in the vicinity of the integrated circuit chip, and good global planarity of the polished surface from one edge of the wafer (or substrate) to the other. It is known that the degree of hardness of the polishing pad affects both the local and global planarity. A hard polishing pad typically has good global planarity, but poor local planarity, whereas a soft polishing pad typically has good local planarity, but poor global planarity.
The inventors have observed that the periphery of the wafer is polished more than the interior of the wafer. It was initially thought by the inventors that this effect was due to the leading edge of the wafer carrier digging into a soft polishing pad while it is being rotated during the polishing process. Attempts to remedy this problem by increasing the hardness of the pad have not been wholly successful.
Accordingly, there is a need to address this uneven polishing problem.